* circuit for Lab#1, parts D thru I 
.include "/mit/6.004/jsim/nominal.jsim" 
.include "/mit/6.004/jsim/lab1checkoff.jsim"
* 2-input NAND: inputs are A and B, output is Z 
.subckt nand2 a b z 
MPD1 z a 1 0 NENH sw=8 sl=1 
MPD2 1 b 0 0 NENH sw=8 sl=1
MPU1 z a vdd vdd PENH sw=10 sl=1
MPU2 z b vdd vdd PENH sw=10 sl=1 
.ends 

* INVERTER: input is A, output is Z 
.subckt inv a z 
MPD1 z a 0 0 NENH sw=16 sl=1 
MPU1 z a vdd vdd PENH sw=16 sl=1 
.ends


.subckt XYZZY A B C Z
MPD1 Z A pdn 0 NENH sw=16 sl=1
MPD2 Z B pdn 0 NENH sw=16 sl=1
MPD3 pdn C 0 0 NENH sw=16 sl=1
MPU1 Z C vdd vdd PENH sw=16 sl=1
MPU2 Z B pun vdd PENH sw=16 sl=1
MPU3 pun A vdd vdd PENH sw=16 sl=1
.ends