.include "/mit/6.004/jsim/nominal.jsim" 
.include "/mit/6.004/jsim/8clocks.jsim" 
.include "/mit/6.004/jsim/lab2checkoff.jsim" 
.options vih=2.6 vil=0.6

* 2-input NAND: inputs are A and B, output is Z 
.subckt nand2 a b z 
MPD1 z a 1 0 NENH sw=8 sl=1 
MPD2 1 b 0 0 NENH sw=8 sl=1
MPU1 z a vdd vdd PENH sw=10 sl=1
MPU2 z b vdd vdd PENH sw=10 sl=1 
.ends 

* 3-input NAND: inputs are A, B, C, output is Z 
.subckt nand3 a b c z 
MPD1 z a 1 0 NENH sw=8 sl=1 
MPD2 1 b 2 0 NENH sw=8 sl=1
MPD3 2 c 0 0 NENH sw=8 sl=1
MPU1 z a vdd vdd PENH sw=10 sl=1
MPU2 z b vdd vdd PENH sw=10 sl=1 
MPU3 z c vdd vdd PENH sw=10 sl=1 
.ends 

* 2-input NOR: inputs are A and B, output is Z 
.subckt nor2 a b z 
MPD1 z a 0 0 NENH sw=8 sl=1 
MPD2 z b 0 0 NENH sw=8 sl=1
MPU1 1 a vdd vdd PENH sw=10 sl=1
MPU2 z b 1 vdd PENH sw=10 sl=1 
.ends 

* 2-input XOR: inputs A, B, output Z
.subckt xor2 a b z
XNOR a b anorb nor2
MPD1 z a pdn 0 NENH sw=8 sl=1
MPD2 pdn b 0 0 NENH sw=8 sl=1
MPD3 z anorb 0 0 NENH sw=8 sl=1
MPU1 z anorb pun vdd PENH sw=10 sl=1
MPU2 pun a vdd vdd PENH sw=10 sl=1
MPU3 pun b vdd vdd PENH sw=10 sl=1
.ends

* 2-input XNOR: inputs A, B, output Z
.subckt xnor2 a b z
XNAND a b anandb nand2
MPD1 z anandb pdn 0 NENH sw=8 sl=1
MPD2 pdn a 0 0 NENH sw=8 sl=1
MPD3 pdn b 0 0 NENH sw=8 sl=1
MPU1 z anandb vdd vdd PENH sw=10 sl=1
MPU2 z a pun vdd PENH sw=10 sl=1
MPU3 pun b vdd vdd PENH sw=10 sl=1
.ends

* INVERTER: input is A, output is Z 
.subckt inv a z 
MPD1 z a 0 0 NENH sw=8 sl=1 
MPU1 z a vdd vdd PENH sw=10 sl=1 
.ends

* FULL-ADDER: input A, B, Cin, outputs S, Cout
.subckt fulladder a b cin s cout
XXOR1 a b 1 xor2
XXOR2 1 cin s xor2
XNAND1 a b 2 nand2
XNAND2 a cin 3 nand2
XNAND3 b cin 4 nand2
XNAND4 2 3 4 cout nand3
.ends

.subckt ADDER4 a3 a2 a1 a0 b3 b2 b1 b0 s4 s3 s2 s1 s0
XFA0 a0 b0 0 s0 c0 fulladder
XFA1 a1 b1 c0 s1 c1 fulladder
XFA2 a2 b2 c1 s2 c2 fulladder
XFA3 a3 b3 c2 s3 s4 fulladder
.ends


*Xtestm clk1 clk2 clk3 s cout fulladder
*.tran 100n
*.plot L(clk1)
*.plot L(clk2)
*.plot L(clk3)
*.plot L(s)
*.plot L(cout)
*.plot L(cout,s)