.include "/mit/6.004/jsim/nominal.jsim" .include "/mit/6.004/jsim/stdcell.jsim" .include "/mit/6.004/jsim/lab6checkoff.jsim" .subckt fa a b c s cout X1 a b 1 xor2 X2 1 c s xor2 X3 a b 2 nand2 X4 b c 3 nand2 X5 a c 4 nand2 X6 2 3 4 cout nand3 .ends .subckt connector a b .connect a b .ends .subckt alu alufn[5:0] A[31:0] B[31:0] alu[31:0] z v n XASxor B[31:0] alufn0#32 XB[31:0] xor2 XASfa A[31:0] XB[31:0] AScin[31:0] S[31:0] AScout[31:0] fa .connect AScin0 alufn0 XASconnect AScin[31:1] AScout[30:0] connector .connect n S31 XASv0 S31 invS31 inverter XASv1 A31 invA31 inverter XASv2 XB31 invXB31 inverter XASv3 A31 XB31 invS31 ASv1 and3 XASv4 invA31 invXB31 S31 ASv2 and3 XASv5 ASv1 ASv2 v or2 XASn0 S[7:0] S[15:8] S[23:16] S[31:24] ASn[7:0] or4 XASn1 ASn[1:0] ASn[3:2] ASn[5:4] ASn[7:6] ASn[9:8] or4 XASn2 ASn9 ASn8 z nor2 .connect GND 0 XC0 n v Clt xor2 XC1 Clt Z Cle or2 XC2 alufn1 alufn2 GND z Clt Cle C0 mux4 XC3 C[31:1] constant0 XB0 A[31:0] B[31:0] alufn0#32 alufn1#32 alufn2#32 alufn3#32 BOOLE[31:0] mux4 XSLW0 B4#16 A[31:16] A[15:0] SLW[31:16] mux2 XSLW1 B4#16 A[15:0] GND#16 SLW[15:0] mux2 XSLX0 B3#24 SLW[31:8] SLW[23:0] SLX[31:8] mux2 XSLX1 B3#8 SLW[7:0] GND#8 SLX[7:0] mux2 XSLY0 B2#28 SLX[31:4] SLX[27:0] SLY[31:4] mux2 XSLY1 B2#4 SLX[3:0] GND#4 SLY[3:0] mux2 XSLZ0 B1#30 SLY[31:2] SLY[29:0] SLZ[31:2] mux2 XSLZ1 B1#2 SLY[1:0] GND#2 SLZ[1:0] mux2 XSLF0 B0#31 SLZ[31:1] SLZ[30:0] SLF[31:1] mux2 XSLF1 B0 SLZ0 GND SLF0 mux2 XSR alufn1 GND A31 RSV mux2 XSRW0 B4#16 A[31:16] RSV#16 SRW[31:16] mux2 XSRW1 B4#16 A[15:0] A[31:16] SRW[15:0] mux2 XSRX0 B3#8 SRW[31:24] RSV#8 SRX[31:24] mux2 XSRX1 B3#24 SRW[23:0] SRW[31:8] SRX[23:0] mux2 XSRY0 B2#4 SRX[31:28] RSV#4 SRY[31:28] mux2 XSRY1 B2#28 SRX[27:0] SRX[31:4] SRY[27:0] mux2 XSRZ0 B1#2 SRY[31:30] RSV#2 SRZ[31:30] mux2 XSRZ1 B1#30 SRY[29:0] SRY[31:2] SRZ[29:0] mux2 XSRF0 B0 SRZ31 RSV SRF31 mux2 XSRF1 B0#31 SRZ[30:0] SRZ[31:1] SRF[30:0] mux2 XS0 alufn0#32 SLF[31:0] SRF[31:0] SO[31:0] mux2 XML0 A[31:0] B0#32 MFAa[31:0] and2 .connect MFAa0 P0 XML1 A[30:0] B1#31 MFA0B[31:1] and2 .connect MFA0C1 GND XMF1 MFAa[31:1] MFA0B[31:1] MFA0C[31:1] MFA1A[31:1] MFA0C[32:2] fa .connect MFA1A1 P1 XML2 A[29:0] B2#30 MFA1B[31:2] and2 .connect MFA1C2 GND XMF2 MFA1A[31:2] MFA1B[31:2] MFA1C[31:2] MFA2A[31:2] MFA1C[32:3] fa .connect MFA2A2 P2 XML3 A[28:0] B3#29 MFA2B[31:3] and2 .connect MFA2C3 GND XMF3 MFA2A[31:3] MFA2B[31:3] MFA2C[31:3] MFA3A[31:3] MFA2C[32:4] fa .connect MFA3A3 P3 XML4 A[27:0] B4#28 MFA3B[31:4] and2 .connect MFA3C4 GND XMF4 MFA3A[31:4] MFA3B[31:4] MFA3C[31:4] MFA4A[31:4] MFA3C[32:5] fa .connect MFA4A4 P4 XML5 A[26:0] B5#27 MFA4B[31:5] and2 .connect MFA4C5 GND XMF5 MFA4A[31:5] MFA4B[31:5] MFA4C[31:5] MFA5A[31:5] MFA4C[32:6] fa .connect MFA5A5 P5 XML6 A[25:0] B6#26 MFA5B[31:6] and2 .connect MFA5C6 GND XMF6 MFA5A[31:6] MFA5B[31:6] MFA5C[31:6] MFA6A[31:6] MFA5C[32:7] fa .connect MFA6A6 P6 XML7 A[24:0] B7#25 MFA6B[31:7] and2 .connect MFA6C7 GND XMF7 MFA6A[31:7] MFA6B[31:7] MFA6C[31:7] MFA7A[31:7] MFA6C[32:8] fa .connect MFA7A7 P7 XML8 A[23:0] B8#24 MFA7B[31:8] and2 .connect MFA7C8 GND XMF8 MFA7A[31:8] MFA7B[31:8] MFA7C[31:8] MFA8A[31:8] MFA7C[32:9] fa .connect MFA8A8 P8 XML9 A[22:0] B9#23 MFA8B[31:9] and2 .connect MFA8C9 GND XMF9 MFA8A[31:9] MFA8B[31:9] MFA8C[31:9] MFA9A[31:9] MFA8C[32:10] fa .connect MFA9A9 P9 XML10 A[21:0] B10#22 MFA9B[31:10] and2 .connect MFA9C10 GND XMF10 MFA9A[31:10] MFA9B[31:10] MFA9C[31:10] MFA10A[31:10] MFA9C[32:11] fa .connect MFA10A10 P10 XML11 A[20:0] B11#21 MFA10B[31:11] and2 .connect MFA10C11 GND XMF11 MFA10A[31:11] MFA10B[31:11] MFA10C[31:11] MFA11A[31:11] MFA10C[32:12] fa .connect MFA11A11 P11 XML12 A[19:0] B12#20 MFA11B[31:12] and2 .connect MFA11C12 GND XMF12 MFA11A[31:12] MFA11B[31:12] MFA11C[31:12] MFA12A[31:12] MFA11C[32:13] fa .connect MFA12A12 P12 XML13 A[18:0] B13#19 MFA12B[31:13] and2 .connect MFA12C13 GND XMF13 MFA12A[31:13] MFA12B[31:13] MFA12C[31:13] MFA13A[31:13] MFA12C[32:14] fa .connect MFA13A13 P13 XML14 A[17:0] B14#18 MFA13B[31:14] and2 .connect MFA13C14 GND XMF14 MFA13A[31:14] MFA13B[31:14] MFA13C[31:14] MFA14A[31:14] MFA13C[32:15] fa .connect MFA14A14 P14 XML15 A[16:0] B15#17 MFA14B[31:15] and2 .connect MFA14C15 GND XMF15 MFA14A[31:15] MFA14B[31:15] MFA14C[31:15] MFA15A[31:15] MFA14C[32:16] fa .connect MFA15A15 P15 XML16 A[15:0] B16#16 MFA15B[31:16] and2 .connect MFA15C16 GND XMF16 MFA15A[31:16] MFA15B[31:16] MFA15C[31:16] MFA16A[31:16] MFA15C[32:17] fa .connect MFA16A16 P16 XML17 A[14:0] B17#15 MFA16B[31:17] and2 .connect MFA16C17 GND XMF17 MFA16A[31:17] MFA16B[31:17] MFA16C[31:17] MFA17A[31:17] MFA16C[32:18] fa .connect MFA17A17 P17 XML18 A[13:0] B18#14 MFA17B[31:18] and2 .connect MFA17C18 GND XMF18 MFA17A[31:18] MFA17B[31:18] MFA17C[31:18] MFA18A[31:18] MFA17C[32:19] fa .connect MFA18A18 P18 XML19 A[12:0] B19#13 MFA18B[31:19] and2 .connect MFA18C19 GND XMF19 MFA18A[31:19] MFA18B[31:19] MFA18C[31:19] MFA19A[31:19] MFA18C[32:20] fa .connect MFA19A19 P19 XML20 A[11:0] B20#12 MFA19B[31:20] and2 .connect MFA19C20 GND XMF20 MFA19A[31:20] MFA19B[31:20] MFA19C[31:20] MFA20A[31:20] MFA19C[32:21] fa .connect MFA20A20 P20 XML21 A[10:0] B21#11 MFA20B[31:21] and2 .connect MFA20C21 GND XMF21 MFA20A[31:21] MFA20B[31:21] MFA20C[31:21] MFA21A[31:21] MFA20C[32:22] fa .connect MFA21A21 P21 XML22 A[9:0] B22#10 MFA21B[31:22] and2 .connect MFA21C22 GND XMF22 MFA21A[31:22] MFA21B[31:22] MFA21C[31:22] MFA22A[31:22] MFA21C[32:23] fa .connect MFA22A22 P22 XML23 A[8:0] B23#9 MFA22B[31:23] and2 .connect MFA22C23 GND XMF23 MFA22A[31:23] MFA22B[31:23] MFA22C[31:23] MFA23A[31:23] MFA22C[32:24] fa .connect MFA23A23 P23 XML24 A[7:0] B24#8 MFA23B[31:24] and2 .connect MFA23C24 GND XMF24 MFA23A[31:24] MFA23B[31:24] MFA23C[31:24] MFA24A[31:24] MFA23C[32:25] fa .connect MFA24A24 P24 XML25 A[6:0] B25#7 MFA24B[31:25] and2 .connect MFA24C25 GND XMF25 MFA24A[31:25] MFA24B[31:25] MFA24C[31:25] MFA25A[31:25] MFA24C[32:26] fa .connect MFA25A25 P25 XML26 A[5:0] B26#6 MFA25B[31:26] and2 .connect MFA25C26 GND XMF26 MFA25A[31:26] MFA25B[31:26] MFA25C[31:26] MFA26A[31:26] MFA25C[32:27] fa .connect MFA26A26 P26 XML27 A[4:0] B27#5 MFA26B[31:27] and2 .connect MFA26C27 GND XMF27 MFA26A[31:27] MFA26B[31:27] MFA26C[31:27] MFA27A[31:27] MFA26C[32:28] fa .connect MFA27A27 P27 XML28 A[3:0] B28#4 MFA27B[31:28] and2 .connect MFA27C28 GND XMF28 MFA27A[31:28] MFA27B[31:28] MFA27C[31:28] MFA28A[31:28] MFA27C[32:29] fa .connect MFA28A28 P28 XML29 A[2:0] B29#3 MFA28B[31:29] and2 .connect MFA28C29 GND XMF29 MFA28A[31:29] MFA28B[31:29] MFA28C[31:29] MFA29A[31:29] MFA28C[32:30] fa .connect MFA29A29 P29 XML30 A[1:0] B30#2 MFA29B[31:30] and2 .connect MFA29C30 GND XMF30 MFA29A[31:30] MFA29B[31:30] MFA29C[31:30] MFA30A[31:30] MFA29C[32:31] fa .connect MFA30A30 P30 XML31 A[0:0] B31#1 MFA30B[31:31] and2 .connect MFA30C31 GND XMF31 MFA30A[31:31] MFA30B[31:31] MFA30C[31:31] MFA31A[31:31] MFA30C[32:32] fa .connect MFA31A31 P31 Xam alufn1#32 S[31:0] P[31:0] SP[31:0] mux2 Xout alufn4#32 alufn5#32 SP[31:0] BOOLE[31:0] SO[31:0] C[31:0] alu[31:0] mux4 .ends .subckt beta clk reset ia[31:0] ie[31:0] ma[31:0] moe mrd[31:0] wr mwd[31:0] .connect GND 0 Xtmp id[31:0] GND#32 connector Xpcmux reset#32 pcinc[31:0] GND#32 pcmuxout[31:0] mux2 Xpcreg pcmuxout[31:0] clk#32 pc[31:0] dreg Xpincc pc[1:0] pcinc[1:0] connector Xpinca1 pc2 vdd GND pcinc2 pccar2 fa Xpinca2 pc[31:3] GND#29 pccar[30:2] pcinc[31:3] pccar[31:3] fa Ximcon pc[31:0] ia[31:0] connector Xregfile vdd 0 0 ie[20:16] adata[31:0] + vdd 0 0 ra2mux[4:0] bdata[31:0] + 0 clk werf waddr[4:0] wdata[31:0] + $memory width=32 nlocations=31 Xra2mux ra2sel#5 ie[15:11] ie[25:21] ra2mux[4:0] mux2 Xwacon ie[25:21] waddr[4:0] connector Xra1r311 ie[20:17] ra1r311 and4 Xra1r312 ra1r311 ie16 ra1r31 and2 Xra1r31mux ra1r31#32 adata[31:0] GND#32 adatamux[31:0] mux2 Xra2r311 ra2mux[4:1] ra2r311 and4 Xra2r312 ra2r311 ra2mux0 ra2r31 and2 Xra2r31mux ra2r31#32 bdata[31:0] GND#32 bdatamux[31:0] mux2 Xbsel1 bsel#16 bdatamux[31:16] ie15#16 bselmux[31:16] mux2 Xbsel2 bsel#16 bdatamux[15:0] ie[15:0] bselmux[15:0] mux2 Xalu alufn[5:0] adatamux[31:0] bselmux[31:0] alu[31:0] z v n alu Xmadcon alu[31:0] ma[31:0] connector Xwdsel wdsel#32 alu[31:0] mrd[31:0] wdata[31:0] mux2 Xmwdcon bdatamux[31:0] mwd[31:0] connector Xctl vdd 0 0 ie[31:26] + alufn[5:0] werf bsel wdsel xwr ra2sel moe + $memory width=12 nlocations=64 contents=( + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000000000 // 0b000000 + 0b000000000000 // 0b000001 + 0b000000111001 // 0b011000 ld + 0b000000010110 // 0b011001 st + 0b000000000000 // 0b011010 + 0b000000000000 // 0b011011 jmp + 0b000000000000 // 0b011100 + 0b000000000000 // 0b011101 beq + 0b000000000000 // 0b011110 bne + 0b000000000000 // 0b011111 ldr + 0b000000100000 // 0b100000 add + 0b000001100000 // 0b100001 sub + 0b000010100000 // 0b100010 mul + 0b000000000000 // 0b100011 div + 0b110011100000 // 0b100100 cmpeq + 0b110101100000 // 0b100101 cmplt + 0b110111100000 // 0b100110 cmple + 0b000000000000 // 0b100111 + 0b011000100000 // 0b101000 and + 0b011110100000 // 0b101001 or + 0b010110100000 // 0b101010 xor + 0b000000000000 // 0b101011 + 0b100000100000 // 0b101100 shl + 0b100001100000 // 0b101101 shr + 0b100011100000 // 0b101110 sra + 0b000000000000 // 0b101111 + 0b000000110000 // 0b110000 addc + 0b000001110000 // 0b100001 sub + 0b000010110000 // 0b100010 mul + 0b000000000000 // 0b100011 div + 0b110011110000 // 0b100100 cmpeq + 0b110101110000 // 0b100101 cmplt + 0b110111110000 // 0b100110 cmple + 0b000000000000 // 0b100111 + 0b011000110000 // 0b101000 and + 0b011110110000 // 0b101001 or + 0b010110110000 // 0b101010 xor + 0b000000000000 // 0b101011 + 0b100000110000 // 0b101100 shl + 0b100001110000 // 0b101101 shr + 0b100011110000 // 0b101110 sra + 0b000000000000 // 0b101111 + ) Xmwemux reset xwr GND wr mux2 .ends