| | | | | | | _________________ -| |- -| |- -| |- -| CYPRESS |- -| |- -| |- Warp VHDL Synthesis Compiler: Version 4 IR x95 -| |- Copyright (C) 1991, 1992, 1993, |_______________| 1994, 1995, 1996, 1997, 1998 Cypress Semiconductor | | | | | | | ====================================================================== Compiling: lab1.vhd Options: -o2 -ygs -fP -v10 -dc20v8 -pPALCE20V8-7PC lab1.vhd ====================================================================== vhdlfe V4 IR x95: VHDL parser Thu Sep 11 18:43:09 2003 Library 'work' => directory 'lc20v8' Linking '/mit/6.111-nfs/warp4.3/lib/common/work/cypress.vif'. Library 'ieee' => directory '/mit/6.111-nfs/warp4.3/lib/ieee/work' Linking '/mit/6.111-nfs/warp4.3/lib/ieee/work/stdlogic.vif'. vhdlfe: No errors. tovif V4 IR x95: High-level synthesis Thu Sep 11 18:43:09 2003 Linking '/mit/6.111-nfs/warp4.3/lib/common/work/cypress.vif'. Linking '/mit/6.111-nfs/warp4.3/lib/ieee/work/stdlogic.vif'. tovif: No errors. topld V4 IR x96: Synthesis and optimization Thu Sep 11 18:43:10 2003 Linking '/mit/6.111-nfs/warp4.3/lib/common/work/cypress.vif'. Linking '/mit/6.111-nfs/warp4.3/lib/ieee/work/stdlogic.vif'. ---------------------------------------------------------- Detecting unused logic. ---------------------------------------------------------- ------------------------------------------------------ Alias Detection ------------------------------------------------------ ------------------------------------------------------ Aliased 0 equations, 1 wires. ------------------------------------------------------ ---------------------------------------------------------- Circuit simplification ---------------------------------------------------------- ---------------------------------------------------------- Circuit simplification results: Expanded 0 signals. Turned 0 signals into soft nodes. Maximum expansion cost was set at 10. ---------------------------------------------------------- Created 21 PLD nodes. topld: No errors. ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 DESIGN HEADER INFORMATION (18:43:11) Input File(s): lab1.pla Device : c20v8 Package : PALCE20V8-7PC ReportFile : lab1.rpt Program Controls: None. Signal Requests: GROUP FAST_SLEW ALL Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 OPTIMIZATION OPTIONS (18:43:11) Messages: Information: Process virtual 'jkffD' ... expanded. Information: Process virtual 'tffD' ... expanded. Information: Optimizing logic using best output polarity for signals: x0 x1 tff.D jkff.D ql qh Information: Selected logic optimization OFF for signals: x2 dff.D dff.C tff.C jkff.C Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: MINOPT.EXE 11/NOV/97 [v4.02 ] 4 IR x95 LOGIC MINIMIZATION (18:43:11) Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Optimizer Software: DSGNOPT.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 OPTIMIZATION OPTIONS (18:43:11) Messages: Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 DESIGN EQUATIONS (18:43:11) /x0 = /a0 * /a1 * /a2 + /a3 * a4 + a2 * /a3 x1 = a3 * /a4 + a2 * /a4 x2 = a4 dff.D = a0 dff.C = ffclk tff.D = a1 * /tff.Q + /a1 * tff.Q tff.C = ffclk jkff.D = a2 * /jkff.Q + /a3 * jkff.Q jkff.C = ffclk /ql = data * /r * qh + /latchclk * /r * qh /qh = /data * /s * ql + /latchclk * /s * ql Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 DESIGN RULE CHECK (18:43:11) Messages: None. Summary: Error Count = 0 Warning Count = 0 Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 DESIGN SIGNAL PLACEMENT (18:43:12) Messages: Information: All signals pre-placed in user design. C20V8C __________________________________________ ffclk =| 1| |24|* not used a0 =| 2| |23|* not used a1 =| 3| |22|= qh a2 =| 4| |21|= ql a3 =| 5| |20|= jkff a4 =| 6| |19|= tff latchclk =| 7| |18|= dff data =| 8| |17|= x2 s =| 9| |16|= x1 r =|10| |15|= x0 not used *|11| |14|* not used not used *|12| |13|* not used __________________________________________ Summary: Error Count = 0 Warning Count = 0 Completed Successfully Information: Checking for duplicate NODE logic. ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 RESOURCE ALLOCATION (18:43:12) Information: Macrocell Utilization. Description Used Max ______________________________________ | Dedicated Inputs | 9 | 12 | | Clock/Inputs | 1 | 1 | | Enable/Inputs | 0 | 1 | | Output Macrocells | 8 | 8 | ______________________________________ 18 / 22 = 81 % Information: Output Logic Product Term Utilization. Node# Output Signal Name Used Max ________________________________________ | 15 | x0 | 3 | 8 | | 16 | x1 | 2 | 8 | | 17 | x2 | 1 | 8 | | 18 | dff | 1 | 8 | | 19 | tff | 2 | 8 | | 20 | jkff | 2 | 8 | | 21 | ql | 2 | 8 | | 22 | qh | 2 | 8 | ________________________________________ 15 / 64 = 23 % Completed Successfully ---------------------------------------------------------------------------- PLD Compiler Software: PLA2JED.EXE 19/JUN/1998 [v4.02 ] 4 IR x96 JEDEC ASSEMBLE (18:43:12) Messages: Information: Output file 'lab1.jed' created. Summary: Error Count = 0 Warning Count = 0 Completed Successfully at 18:43:12