-- This comment is before the library and use clauses.
library ieee;
use ieee.std_logic_1164.all;
-- here is the entity
entity lab1 is
  port (ffclk, a0, a1, a2, a3, a4, latchclk, data, s, r : in std_logic;
        x0, x1, x2 : out std_logic;
        dff, tff, jkff, ql, qh: buffer std_logic);
attribute pin_numbers of lab1:entity is
  " ffclk:1 a0:2 a1:3 a2:4 a3:5 a4:6 latchclk:7 data:8 s:9 r:10" &
  " x0:15 x1:16 x2:17 " &
  " dff:18 tff:19 jkff:20 ql:21 qh:22 ";
  -- don't forget to ground pin 13
-- having these two attributes makes the equations easier to understand
-- it also ensures symmetry
attribute synthesis_off of qh:signal is true;
attribute synthesis_off of ql:signal is true;
end lab1;
-- here is the architecture
architecture behavioral of lab1 is
begin
  -- x2, x1, x0 is (supposed to be) the integer part of
  -- the square root of a4, a3, a2, a1, a0
  -- concurent statements implementing x2, x1, and x0
  x2 <= a4;
  x1 <= (not a4) and (a3 or a2);
--  x0 <= not (((not a4) or a3)(a3 or (not a2)) and (a3 or a1 or a0);
  x0 <= (a3 and a1) or (a3 and a0) or (a3 and a2) or
        ((not a4) and (not a2) and a0) or ((not a4) and (not a2) and a1);
  -- a process implementing the three flip-flops
  process (ffclk) begin
    if rising_edge(ffclk) then
      dff <= a0;
      tff <= a1 xor tff;
      jkff <= (a2 and (not jkff)) or ((not a3) and jkff);
      -- note that extra parentheses are ok
    end if;
  end process;
  -- concurent statements implementing qh and ql
  ql <= r or (not qh) or (latchclk and (not data));
  qh <= s or (not ql) or (latchclk and data);
end behavioral;