-- leveltopulse.vhd: level to pulse unit
-- Dan R. K. Ports    <drkp@mit.edu>
-- 6.111 Lab 2, 2003/10/01

library ieee;
use ieee.std_logic_1164.all;

entity leveltopulse is
  
  port (
    level : in  std_logic;           
    clk   : in  std_logic;
    pulse : out std_logic);

end leveltopulse;

architecture behavioral of leveltopulse is

  signal x, y, z : std_logic := '0';
  
begin  -- behavioral

  process (clk)
  begin  -- process
    if rising_edge(clk) then
      x <= level;
      y <= x;
      z <= y;
    end if;
  end process;

  pulse <= (y and (not z));
  
end behavioral;