-- Don't forget to "erase" both your FPGAs before programming them.
-- Read the warning on the FPGA handout.
-- Access it via the web page if you don't have a copy handy.
-- You probably want to assign pins using MAX+plusII or
-- by editing the xxx.acf file.  See the Beginner's Guide to MAX+PlusII.
-- This comment is before the library and use clauses.
library ieee;
use ieee.std_logic_1164.all;
-- here is the entity
entity fsm is
  port (reset, l0, l1, f0, f1 : in std_logic;
	gosync, auxsync, wreqlatch, exp, clk : in std_logic;
--        rs, ys, gs, rm, ym, gm : out std_logic;
	a0, a1, nwe, start_timer : out std_logic);

end fsm;
-- here is the architcture
architecture state_machine of fsm is
  -- this is the declaration of signals.
  type StateType is (rmgs, rmys, gmrs, ymrs, walk, rmrs, ymrs1);
  -- Should you want to specify exact state encodings for enum types
  -- This one is for the signals rm, ym, gm, rs, ys, gs, extra_state_bit
  -- You could define constants for the states and not use enum_encoding.
  attribute enum_encoding : string;
  attribute enum_encoding of StateType:
    type is "1000010 1000100 0011000 0101000 1101100 1001000 0101001";
  signal p_s, n_s : StateType;
  -- here is the body of the architecture
begin
  -- the order is irrelevant, all are computed concurrently
  fsm:process(p_s, exp)
  begin
    case p_s is
      when rmgs =>  
        if exp = '1' then n_s <= rmys;
	else n_s <= rmgs;
	end if;
      when others =>    n_s <= walk; -- or your favorite state
    end case;
  end process fsm;

  state_clocked:process(clk, exp)
  begin
    -- if (clk'event and clk='1') then
    if rising_edge(clk) then p_s <= n_s;
    end if;
    if exp = '1' then start_timer <= '1';
    else start_timer <= '0';
    end if;
  end process state_clocked;

end architecture state_machine; --"architecture" is optional; for clarity