-- timer.vhd: programmable count-down timer
-- Dan R. K. Ports   <drkp@mit.edu>
-- 6.111 Lab 2, 2003/10/01

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity timer is
  
  port (
    D                        : in  std_logic_vector(3 downto 0);
    clk, longclk, starttimer : in  std_logic;
    resettimer               : in  std_logic;
    countout                 : out std_logic_vector(3 downto 0);
    expired                  : out std_logic);

end timer;

architecture behavioral of timer is

  signal count : std_logic_vector(3 downto 0);
  signal countzero : std_logic := '1';
  signal counting : std_logic := '0';

begin  -- behavioral

  -- purpose: count down on clock pulses
  -- type   : sequential
  -- inputs : clk, starttimer, longclk
  -- outputs: expired
  process (clk, starttimer)
  begin  -- process

    if rising_edge(clk) then
      if resettimer = '1' then
        count <= D;
        counting <= '0';
        countzero <= '0';
      elsif starttimer = '1' then
        count <= D;
        counting <= '1';
        countzero <= '0';
      elsif count = 0 then
        if countzero = '1' then
          counting <= '0';
	  countzero <= '1';
        else
          countzero <= '1';  
        end if;
      elsif longclk = '1' then
        count <= count - 1;
      else
	count <= count;
      end if;
    end if;
    
  end process;

  expired <= countzero and counting;
  countout <= count;

end behavioral;