-- top.vhd: top-level structure for traffic light controller
-- Dan R. K. Ports   <drkp@mit.edu>
-- 6.111 Lab 2, 2003/10/01

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity top is
  
  port (
    clk, sens, wreq, go, reset, c0, c1, c2, c3 : in    std_logic;
    l0, l1, f0, f1                          : in    std_logic;
    D                                       : inout std_logic_vector(3 downto 0);
    d_gosync, d_senssync, d_resetsync, d_latchreset, d_wreqlatch,
    d_starttimer, d_resettimer, d_longclk, d_expire: out std_logic;
    countout, stateout                      : out std_logic_vector(3 downto 0);
    a0, a1, n_weout, mr, my, mg, sr, sy, sg : out   std_logic);

end top;

architecture behavioral of top is

  component synchronizer
    port (
      clk, syncin : in  std_logic;
      syncout     : out std_logic);
  end component;

  component divider
    port (
      clk, rst : in  std_logic;
      longclk  : out std_logic);
  end component;

  component fsm
    port (
      reset, l0, l1, f0, f1                      : in  std_logic;
      gosync, senssync, wreqlatch, expire, clk   : in  std_logic;
      mr, my, mg, sr, sy, sg                     : out std_logic;
      stateout                           : out std_logic_vector (3 downto 0);
      a0, a1, n_we, latchreset, starttimer, resettimer : out std_logic);
  end component;

  component wrlatch
    port (
      latchset, latchreset : in  std_logic;
      latchout             : out std_logic);
  end component;
  
  component leveltopulse
    port (
      level : in  std_logic;
      clk   : in  std_logic;
      pulse : out std_logic);
  end component;

  component timer
    port (
      D                        : in  std_logic_vector(3 downto 0);
      clk, longclk, starttimer : in  std_logic;
      resettimer               : in  std_logic;
      countout                 : out std_logic_vector(3 downto 0);
      expired                  : out std_logic);
  end component;

  component tribuffer
    port (
      input  : in  std_logic;
      enable : in  std_logic;
      output : out std_logic);
  end component;

  signal gosync, senssync, resetsync, latchreset, wreqlatch : std_logic;
  signal starttimer, resettimer, longclk, expire : std_logic;
  signal n_we, we, tbe : std_logic;
begin  -- behavioral

  GOLTP : leveltopulse port map (
    level => go,
    clk   => clk,
    pulse => gosync);

  SENSSY : synchronizer port map (
    clk     => clk,
    syncin  => sens,
    syncout => senssync);

  RESETLTP : leveltopulse port map (
    level => reset,
    clk   => clk,
    pulse => resetsync);

  WLATCH : wrlatch port map (
    latchset   => wreq,
    latchreset => latchreset,
    latchout   => wreqlatch);

  DIV : divider port map (
    clk     => clk,
    rst   => starttimer,
    longclk => longclk);

  TIM : timer port map (
    D          => D,
    clk        => clk,
    longclk    => longclk,
    starttimer => starttimer,
    resettimer => resettimer,
    countout   => countout,
    expired    => expire);

   STATEMACHINE : fsm port map (
     reset      => resetsync,
     l0         => l0,
     l1         => l1,
     f0         => f0,
     f1         => f1,
     gosync     => gosync,
     senssync   => senssync,
     wreqlatch  => wreqlatch,
     expire     => expire,
     clk        => clk,
     mr         => mr,
     my         => my,
     mg         => mg,
     sr         => sr,
     sy         => sy,
     sg         => sg,
     a0         => a0,
     a1         => a1,
     n_we       => n_we,
     stateout   => stateout,
     latchreset => latchreset,
     starttimer => starttimer,
     resettimer => resettimer);

  T0 : tribuffer port map (
    input  => C0,
    output => D(0),
    enable => tbe);
  T1 : tribuffer port map (
    input  => C1,
    output => D(1),
    enable => tbe);
  T2 : tribuffer port map (
    input  => C2,
    output => D(2),
    enable => tbe);
  T3 : tribuffer port map (
    input  => C3,
    output => D(3),
    enable => tbe);

  we <= not n_we;
  n_weout <= n_we;
  tbe <= we and not clk;


  d_gosync <= gosync;
  d_senssync <= senssync;
  d_resetsync <= resetsync;
  d_latchreset <= latchreset;
  d_wreqlatch <= wreqlatch;
  d_starttimer <= starttimer;
  d_resettimer <= resettimer;
  d_longclk <= longclk;
  d_expire <= expire;
  
end behavioral;