-- divider.vhd: 10 MHz to 44.248 kHz clock divider
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 Lab 2, 2003/10/01
-- Modified for 6.111 Lab 3, 2003/10/15

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity divider is
  
  port (
    clk, rst : in  std_logic;
    longclk  : out std_logic);

end divider;

architecture behavioral of divider is

  signal longclkstate : std_logic := '0';
  signal count : std_logic_vector(24 downto 0);
  
begin  -- behavioral

  -- purpose: generate output pulse when counter reaches 1000000
  -- type   : sequential
  -- inputs : clk, rst
  -- outputs: longclk
  process (clk, rst)
  begin  -- process
    if rst = '1' then           -- asynchronous reset (active high)
      count <= (others => '0');
    elsif clk'event and clk = '1' then  -- rising clock edge
      count <= count + 1;
    if count = 225 then
      longclkstate <= '1';
    elsif count = 226 then
      count <= (others => '0');
      longclkstate <= '0';
    end if;
    end if;

    
  end process;

  longclk <= longclkstate;

end behavioral;