-- multiplier.vhd: 8-bit synchronous multiplier
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 Lab 3, 2003/10/22

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity multiplier is
  
  port (
    a, b       : in  std_logic_vector(7 downto 0);  -- sign/mag
    prod       : out std_logic_vector(14 downto 0); -- sign/mag
    clk, start : in  std_logic;
    busy       : out std_logic);

end multiplier;

architecture behavioral of multiplier is

  signal sreg, hreg : std_logic_vector(14 downto 0);
  signal accumulator : std_logic_vector(14 downto 0);
  signal count : std_logic_vector(3 downto 0);
  signal sign : std_logic;
  
begin  -- behavioral

  -- purpose: perform multiplication
  -- type   : sequential
  -- inputs : clk, start, a, b
  -- outputs: accumulator, count
  multiply: process (clk, start)
  begin  -- process multiply

    if rising_edge(clk) then
      if start = '1' then
        count <= "0110";
        sreg <= "0000000" & a(6 downto 0) & '0';
        hreg <= "000000000" & b(6 downto 1);
        sign <= a(7) xor b(7);
        if b(0) = '1' then
          accumulator <= "0000000" & a;
        else
          accumulator <= (others => '0');
        end if;
      elsif count > 0 then
        count <= count - 1;
        if hreg(0) = '1' then
          accumulator <= accumulator + sreg;
        end if;
        hreg <= '0' & hreg(14 downto 1);
        sreg <= sreg(13 downto 0) & '0';
      end if;
    end if;
    
  end process multiply;

  busy <= '0' when count = 0 else '1';
  prod <= sign & accumulator(13 downto 0);
  
end behavioral;