-- top-analog.vhd: top level structural definition for analog checkoff
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 Lab 3, 2003/10/15

library ieee;
use ieee.std_logic_1164.all;

entity top is
  port (
    n_ADCEnable, ADCRead : out   std_logic;  -- ADC control
    ADCStatus            : in    std_logic;  -- ADC status
    n_DACEnable          : out   std_logic;  -- DAC control
    reset                : in    std_logic;
    clk                  : in    std_logic;
    D                    : inout std_logic_vector(7 downto 0)); 
                           -- ADC/DAC data bus

end top;

architecture structural of top is

  component fsm
     port (
    n_ADCEnable, ADCRead : out   std_logic;  -- ADC control
    ADCStatus            : in    std_logic;  -- ADC status
    n_DACEnable          : out   std_logic;  -- DAC control
    reset                : in    std_logic;
    clk                  : in    std_logic;
    timerClk             : in    std_logic;
    Dout                 : out   std_logic_vector(7 downto 0);
    D                    : inout std_logic_vector(7 downto 0)); 
                           -- ADC/DAC data bus
  end component;

  component divider
    port (
      clk, rst : in  std_logic;
      longclk  : out std_logic);
  end component;

  signal timerClk : std_logic;
  
begin  -- structural

  controller : fsm port map (
    n_ADCEnable => n_ADCEnable,
    ADCRead     => ADCRead,
    n_DACEnable => n_DACEnable,
    ADCStatus   => ADCStatus,
    reset       => reset,
    clk         => clk,
    timerClk    => timerClk,
    D           => D);

  div : divider port map (
    clk     => clk,
    rst     => reset,
    longclk => timerClk);

end structural;