-- top.vhd: top-level structural definition
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 Lab 3, 2003/10/22

library ieee;
use ieee.std_logic_1164.all;
library lpm;

entity top is
  port (
    n_ADCEnable, ADCRead : out   std_logic;  -- ADC control
    ADCStatus            : in    std_logic;  -- ADC status
    n_DACEnable          : out   std_logic;  -- DAC control
    reset                : in    std_logic;
    clk                  : in    std_logic;
    impswitches          : in    std_logic_vector(3 downto 0);
    bypass               : in    std_logic;
    D                    : inout std_logic_vector(7 downto 0)); 
                                 -- ADC/DAC data bus

end top;

architecture structural of top is

  component rom
        PORT
        (
                address         : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
  end component;

  component ram
        PORT
        (
                data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                address         : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                we              : IN STD_LOGIC  := '1';
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
  end component;
  
  component divider
    port (
      clk, rst : in  std_logic;
      longclk  : out std_logic);
  end component;

  component convolver
   port (
    clk               : in  std_logic;
    start             : in  std_logic;
    reset             : in  std_logic;
    busy              : out std_logic;
    inputaddr         : in  std_logic_vector(3 downto 0);
    multstart         : out std_logic;
    multbusy          : in  std_logic;
    multresult        : in  std_logic_vector(14 downto 0);
    romaddr, ramaddr  : out std_logic_vector(3 downto 0);
    result            : out std_logic_vector(7 downto 0));
  end component;

  component fsm
    port (
    n_ADCEnable, ADCRead : out   std_logic;  -- ADC control
    ADCStatus            : in    std_logic;  -- ADC status
    n_DACEnable          : out   std_logic;  -- DAC control
    reset                : in    std_logic;
    clk                  : in    std_logic;
    timerClk             : in    std_logic;
    convolverstart       : out   std_logic;
    convolverbusy        : in    std_logic;
    convolverresult      : in    std_logic_vector(7 downto 0);
    convolverstartaddr   : out   std_logic_vector(3 downto 0);
    ramaddr              : out   std_logic_vector(3 downto 0);
    ramdata              : out   std_logic_vector(7 downto 0);
    ramwe                : out   std_logic;
    bypass               : in   std_logic;
    D                    : inout std_logic_vector(7 downto 0));
                                -- ADC/DAC data bus

  end component;

  component multiplier
   port (
    a, b       : in  std_logic_vector(7 downto 0);  -- sign/mag
    prod       : out std_logic_vector(14 downto 0); -- sign/mag
    clk, start : in  std_logic;
    busy       : out std_logic);
  end component;

  component numconv
   generic (
    width : integer := 8);
 
   port (
    input  : in  std_logic_vector(width-1 downto 0);
    output : out std_logic_vector(width-1 downto 0));
  end component;
  
  signal timerClk : std_logic;
  signal convolverstart, convolverbusy : std_logic;
  signal convolverstartaddr : std_logic_vector(3 downto 0);
  signal convolverresult : std_logic_vector(7 downto 0);
  signal ramwe, ramwren : std_logic;
  signal ramwdata, ramrdata, ramdatasm, romdata
                                     : std_logic_vector(7 downto 0);
  signal ramwaddr, ramraddr, ramaddr : std_logic_vector(3 downto 0);
  signal romaddr : std_logic_vector(7 downto 0);
  signal romaddrl : std_logic_vector(3 downto 0);
  signal multstart, multbusy : std_logic;
  signal multresultsm, multresulttc : std_logic_vector(14 downto 0);
  
begin  -- structural

  controller : fsm port map (
    n_ADCEnable => n_ADCEnable, 
    ADCRead     => ADCRead,
    n_DACEnable => n_DACEnable,
    ADCStatus   => ADCStatus,
    reset       => reset,
    clk         => clk,
    timerClk    => timerClk,
    D           => D,
    convolverstart => convolverstart,
    convolverbusy => convolverbusy,
    convolverstartaddr => convolverstartaddr,
    convolverresult =>  convolverresult,
    ramwe => ramwe,
    ramdata => ramwdata,
    bypass => bypass,
    ramaddr => ramwaddr);

  div : divider port map (
    clk     => clk,
    rst     => reset,
    longclk => timerClk);

  conv : convolver port map (
    clk                => clk,
    start              => convolverstart,
    reset              => reset,
    busy               => convolverbusy,
    inputaddr          => convolverstartaddr,
    multstart          => multstart,
    multbusy           => multbusy,
    multresult         => multresulttc,
    romaddr            => romaddrl,
    ramaddr            => ramraddr,
    result             => convolverresult);

  mult : multiplier port map (
    a     => romdata,
    b     => ramdatasm,
    prod  => multresultsm,
    clk   => clk,
    start => multstart,
    busy  => multbusy);

  ramnc : numconv generic map (
    width => 8)
    port map (
      input  => ramrdata,
      output => ramdatasm);

  multnc : numconv generic map (
    width => 15)
    port map (
      input  => multresultsm,
      output => multresulttc);

  raminst : ram port map (
    data      => ramwdata,
    q         => ramrdata,
--    wraddress => ramwaddr,
    address => ramaddr,
--    clock       => clk,
    we      => ramwren);

  rominst : rom port map (
    address => romaddr,
    q       => romdata);

  ramaddr <= ramraddr when convolverbusy = '1' else ramwaddr;
  ramwren <= ramwe and not clk;
  romaddr <= impswitches & romaddrl;
  
end structural;