-- complexmult.vhd: combinational complex multiplier
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/03

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity complexmult is
  
  port (
    are, aim, bre, bim : in  std_logic_vector(7 downto 0);
    prodre, prodim     : out std_logic_vector(15 downto 0));

end complexmult;

architecture structural of complexmult is

  component mult
        PORT
        (
                dataa           : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                datab           : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
                result          : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
        );
  end component;

  signal re1, re2, im1, im2 : std_logic_vector(15 downto 0);
  
begin  -- structural

  mult1 : mult port map (
    dataa  => are,
    datab  => bre,
    result => re1);

  mult2 : mult port map (
    dataa  => aim,
    datab  => bim,
    result => re2);

  mult3 : mult port map (
    dataa  => are,
    datab  => bim,
    result => im1);

  mult4 : mult port map (
    dataa  => aim,
    datab  => bre,
    result => im2);

  prodre <= re1 - re2;
  prodim <= im1 + im2;
  

end structural;