-------------------------------------------------------------------------------
--
-- fftmgrtestjig.vhd: test jig for validating FFT processor with memory mgr
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/05
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity fftmgrtestjig is

    port (
    start, reset, clk         : in    std_logic;
    busy                      : out   std_logic;
    inbufsel, outbufsel       : in    std_logic_vector(1 downto 0);
    treout                    : out   std_logic_vector(7 downto 0);
    databusinout              : out   std_logic_vector(7 downto 0);
    databusoutout             : out   std_logic_vector(7 downto 0);
    inverse                   : in    std_logic;
    ramreqout, ramdoneout     : out   std_logic;
    ramwe                     : out   std_logic);
  
end fftmgrtestjig;

architecture structural of fftmgrtestjig is

  component fft
    port (
    start, reset, clk         : in    std_logic;
    testaddrbus                   : out   std_logic_vector(6 downto 0);
    databusout                   : out std_logic_vector(7 downto 0);
    databusin                   : in std_logic_vector(7 downto 0);
    busy                      : out   std_logic;
    inbufsel, outbufsel       : in    std_logic_vector(1 downto 0);
    treout                    : out   std_logic_vector(7 downto 0);
    databusinout              : out   std_logic_vector(7 downto 0);
    inverse                   : in    std_logic;
    ramreq                    : out   std_logic;
    ramdone                   : in    std_logic;
    ramwe                     : out   std_logic);

  end component;

  component memmgr

  
    port (
    aaddr, baddr, caddr : in    std_logic_vector(14-1 downto 0);
    adata, bdata, cdata : in    std_logic_vector(8-1 downto 0) := (others => 'Z');
    aq, bq, cq          : out    std_logic_vector(8-1 downto 0) := (others => 'Z');
    awr, bwr, cwr       : in    std_logic;
    clk, reset          : in    std_logic;
    areq, breq, creq    : in    std_logic;
    adone, bdone, cdone : out   std_logic;
    ramaddr             : out   std_logic_vector(14-1 downto 0);
--    ramdata             : inout std_logic_vector(8-1 downto 0) := (others => 'Z');
    ramdatain           : in    std_logic_vector(7 downto 0);
    ramdataout          : out   std_logic_vector(7 downto 0);
    ramwe               : out   std_logic);



  end component;
  
--  component testram
--        PORT
--        (
--                address         : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--                we              : IN STD_LOGIC  := '1';
--                outenab         : IN STD_LOGIC  := '1';
--                dio             : INOUT STD_LOGIC_VECTOR (13 DOWNTO 0)
--        );
--  end component;
--
 component testram
       PORT
       (
               address         : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
               we              : IN STD_LOGIC  := '1';
               data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
               q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
       );
end component;
  
  signal fftaddrbus, addrbus : std_logic_vector(6 downto 0);
  signal aaddr, nulladdr, mgrramaddrbus : std_logic_vector(13 downto 0);
  signal ramdatain, ramdataout, nulldata, bq, cq : std_logic_vector(7 downto 0);
  signal databus, d, q : std_logic_vector(7 downto 0);
  signal fftwe, oe, ramweint, ramreq, ramdone, nullflag, bdone, cdone : std_logic;
  
begin  -- structural


  fftinst : fft port map (
    start     => start,
    reset     => reset,
    clk       => clk,
    testaddrbus   => fftaddrbus,
    databusout   => d,
    databusin => q,
    busy      => busy,
    inbufsel  => inbufsel,
    outbufsel => outbufsel,
    treout    => treout,
    inverse   => inverse,
    databusinout => databusinout,
    ramreq => ramreq,
    ramdone => ramdone,
    ramwe     => fftwe);

  raminst : testram port map (
    address   => addrbus,
    data        => ramdataout,
    q   => ramdatain,
    we        => ramweint);

  mmgr : memmgr port map (
    aaddr      => aaddr,
    adata      => d,
    aq         => q,
    awr        => fftwe,
    clk        => clk,
    reset      => reset,
    areq       => ramreq,
    adone      => ramdone,
    ramaddr    => mgrramaddrbus,
    ramdatain  => ramdatain,
    ramdataout => ramdataout,
    ramwe      => ramweint,
    baddr      => nulladdr,
    caddr      => nulladdr,
    bdata      => nulldata,
    cdata      => nulldata,
    bq         => bq,
    cq         => cq,
    bwr        => nullflag,
    cwr        => nullflag,
    breq       => nullflag,
    creq       => nullflag,
    bdone      => bdone,
    cdone      => cdone);

  oe <= '1';

  ramwe <= ramweint;

  databusoutout <= d;

  nulladdr <= (others => '0');
  nullflag <= '0';
  nulldata <= (others => '0');

  addrbus <= mgrramaddrbus(6 downto 0);
  aaddr <= "0000000" & fftaddrbus;

  ramreqout <= ramreq;
  ramdoneout <= ramdone;
  
end structural;