-------------------------------------------------------------------------------
--
-- memmgrtestjig.vhd: test jig for validating memory manager
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/07
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity memmgrtestjig is

port (
    aaddr, baddr, caddr : in    std_logic_vector(6 downto 0);
    adata, bdata, cdata : in    std_logic_vector(7 downto 0) := (others => 'Z');
    aq, bq, cq          : out    std_logic_vector(7 downto 0) := (others => 'Z');
    awr, bwr, cwr       : in    std_logic;
    clk, reset          : in    std_logic;
    areq, breq, creq    : in    std_logic;
    adone, bdone, cdone : out   std_logic);
--    ramaddr             : out   std_logic_vector(14-1 downto 0);
--    ramdata             : inout std_logic_vector(8-1 downto 0) := (others => 'Z');
--    ramdatain           : in    std_logic_vector(7 downto 0);
--    ramdataout          : out   std_logic_vector(7 downto 0);
--    ramwe               : out   std_logic);
  
end memmgrtestjig;

architecture structural of memmgrtestjig is

  component memmgr

  port (
    aaddr, baddr, caddr : in    std_logic_vector(14-1 downto 0);
    adata, bdata, cdata : in    std_logic_vector(8-1 downto 0) := (others => 'Z');
    aq, bq, cq          : out    std_logic_vector(8-1 downto 0) := (others => 'Z');
    awr, bwr, cwr       : in    std_logic;
    clk, reset          : in    std_logic;
    areq, breq, creq    : in    std_logic;
    adone, bdone, cdone : out   std_logic;
    ramaddr             : out   std_logic_vector(14-1 downto 0);
--    ramdata             : inout std_logic_vector(8-1 downto 0) := (others => 'Z');
    ramdatain           : in    std_logic_vector(7 downto 0);
    ramdataout          : out   std_logic_vector(7 downto 0);
    ramwe               : out   std_logic);

    
  end component;


   component testram
       PORT
       (
               address         : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
               we              : IN STD_LOGIC  := '1';
               data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
               q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
       );
   end component;


  signal address : std_logic_vector(6 downto 0);
  signal data, q : std_logic_vector(7 downto 0);
  signal we : std_logic;
  signal mgraddress : std_logic_vector(13 downto 0);
  signal aaddre, baddre, caddre : std_logic_vector(13 downto 0);
  
begin  -- structural

  aaddre <= "0000000" & aaddr;
  baddre <= "0000000" & baddr;
  caddre <= "0000000" & caddr;
  
  mgr : memmgr port map (
    aaddr       => aaddre,
    baddr      =>  baddre,
    caddr      =>  caddre,
    adata      => adata,
    bdata      => bdata,
    cdata      => cdata,
    aq         => aq,
    bq         => bq,
    cq         => cq,
    awr        => awr,
    bwr        => bwr,
    cwr        => cwr,
    clk        => clk,
    reset      => reset,
    areq       => areq,
    breq       => breq,
    creq       => creq,
    adone      => adone,
    bdone      => bdone,
    cdone      => cdone,
    ramaddr    => mgraddress,
    ramdatain  => q,
    ramdataout => data,
    ramwe      => we);

  raminst : testram port map (
    address => address,
    data    => data,
    q       => q,
    we      => we);

  address <= mgraddress(6 downto 0);

end structural;