-------------------------------------------------------------------------------
-- 
-- synchronizer.vhd: multi-input synchronizer
-- Dan R. K. Ports   <drkp@mit.edu>
-- 6.111 final project, 2003/12/07
-- 
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity synchronizer is
  generic (
    width : integer := 8);
  port (
    clk         : in  std_logic;
    syncin      : in  std_logic_vector(width-1 downto 0),
    syncout     : out std_logic_vector(width-1 downto 0));
end synchronizer;

architecture synchronizer of synchronizer is

begin  -- synchronizer

  -- purpose: synchronize output on rising edge of clock
  -- type   : combinational
  -- inputs : clk
  -- outputs: syncout
  sync: process (clk)
  begin  -- process sync
    if rising_edge(clk) then
      syncout <= syncin;
    end if;
  end process sync;

end synchronizer;