-------------------------------------------------------------------------------
--
-- synchronizer1.vhd: 1-input synchronizer
-- Dan R. K. Ports   <drkp@mit.edu>
-- 6.111 Lab 2, 2003/10/01
-- Modified for 6.111 final project, 2003/12/08
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity synchronizer1 is
  port (
    clk, syncin : in  std_logic;
    syncout     : out std_logic);
end synchronizer1;

architecture synchronizer1 of synchronizer1 is

begin  -- synchronizer1

  -- purpose: synchronize output on rising edge of clock
  -- type   : combinational
  -- inputs : clk
  -- outputs: syncout
  sync: process (clk)
  begin  -- process sync
    if rising_edge(clk) then
      syncout <= syncin;
    end if;
  end process sync;

end synchronizer1;