-- top.vhd: top level structural definition
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/03

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity top is
  
  port (
    clk, reset                                      : in    std_logic;
    n_DACEnable, ADCRead                            : out   std_logic;
    ADCStatus                                       : in    std_logic;
    n_adcramwe, adcntenable                         : out   std_logic;
    fftsending, ifctrenable, ifrdenable, ifwrenable : out   std_logic;
    rdy, ack1                                       : inout std_logic;
    ack2, procsending                               : in    std_logic);

end top;

architecture structural of top is

  component adfsm
      port (
        clk, start           : in  std_logic;
        reset                : in  std_logic;
        timerClk             : in  std_logic;
        busy                 : out std_logic;
        ADCRead, n_DACEnable : out std_logic;
        ADCStatus            : in  std_logic;
        ramwe                : out std_logic;
        cntenable            : out std_logic);
  end component;

  component divider
    port (
      clk, rst : in  std_logic;
      longclk  : out std_logic);
  end component;

  component interfacefsm

    port (
      start                   : in    std_logic;
      reset                   : in    std_logic;
      busy                    : out   std_logic;
      clk                     : in    std_logic;
      fftsending              : out   std_logic;
      procsending             : in    std_logic;
      rdy                     : inout std_logic;
      ack1                    : inout std_logic;
      ack2                    : in    std_logic;
      ctrenable               : out   std_logic;
      readenable, writeenable : out   std_logic);
    
  end component;

  signal timerClk : std_logic;
  signal adcramwe : std_logic;
  signal adstart, ifstart, adbusy, ifbusy : std_logic;
  
begin  -- structural

  div : divider port map (
    clk     => clk,
    reset   => reset,
    longclk => timerClk);

  addafsm : adfsm port map (
    clk         => clk,
    start       => adstart,
    reset       => reset,
    timerClk    => timerClk,
    busy        => adbusy,
    ADCRead     => ADCRead,
    n_DACEnable => n_DACEnable,
    ADCStatus   => ADCStatus,
    ramwe       => adcramwe,
    cntenable   => adcntenable);

  n_adcramwe <= not adcramwe;

  iffsm : interfacefsm port map (
    start       => ifstart,
    reset       => reset,
    busy        => ifbusy,
    clk         => clk,
    fftsending  => fftsending,
    procsending => procsending,
    rdy         => rdy,
    ack1        => ack1,
    ack2        => ack2,
    ctrenable   => ifctrenable,
    readenable  => ifrdenable,
    writeenable => ifwrenable);

  adstart <= not reset;
  ifstart <= not reset;
  
end structural;