-- megafunction wizard: %Dual-port RAM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altdpram -- ============================================================ -- File Name: buff.vhd -- Megafunction Name(s): -- altdpram -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD GENERATED FILE. DO NOT EDIT THIS FILE! -- ************************************************************ -- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- support information, device programming or simulation file, and any other -- associated documentation or information provided by Altera or a partner -- under Altera's Megafunction Partnership Program may be used only to -- program PLD devices (but not masked PLD devices) from Altera. Any other -- use of such megafunction design, net list, support information, device -- programming or simulation file, or any other related documentation or -- information is prohibited for any other purpose, including, but not -- limited to modification, reverse engineering, de-compiling, or use with -- any other silicon devices, unless such use is explicitly licensed under -- a separate agreement with Altera or a megafunction partner. Title to -- the intellectual property, including patents, copyrights, trademarks, -- trade secrets, or maskworks, embodied in any such megafunction design, -- net list, support information, device programming or simulation file, or -- any other related documentation or information provided by Altera or a -- megafunction partner, remains with Altera, the megafunction partner, or -- their respective licensors. No other licenses, including any licenses -- needed under any third party's intellectual property, are provided herein. LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY buff IS PORT ( data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0); wren : IN STD_LOGIC := '1'; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) ); END buff; ARCHITECTURE SYN OF buff IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT altdpram GENERIC ( width : NATURAL; widthad : NATURAL; indata_reg : STRING; wraddress_reg : STRING; wrcontrol_reg : STRING; rdaddress_reg : STRING; rdcontrol_reg : STRING; outdata_reg : STRING; indata_aclr : STRING; wraddress_aclr : STRING; wrcontrol_aclr : STRING; rdaddress_aclr : STRING; rdcontrol_aclr : STRING; outdata_aclr : STRING; lpm_hint : STRING ); PORT ( wren : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); rdaddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0); wraddress : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; BEGIN q <= sub_wire0(7 DOWNTO 0); altdpram_component : altdpram GENERIC MAP ( WIDTH => 8, WIDTHAD => 4, INDATA_REG => "UNREGISTERED", WRADDRESS_REG => "UNREGISTERED", WRCONTROL_REG => "UNREGISTERED", RDADDRESS_REG => "UNREGISTERED", RDCONTROL_REG => "UNREGISTERED", OUTDATA_REG => "UNREGISTERED", INDATA_ACLR => "OFF", WRADDRESS_ACLR => "OFF", WRCONTROL_ACLR => "OFF", RDADDRESS_ACLR => "OFF", RDCONTROL_ACLR => "OFF", OUTDATA_ACLR => "OFF", LPM_HINT => "USE_EAB=ON" ) PORT MAP ( wren => wren, data => data, rdaddress => rdaddress, wraddress => wraddress, q => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: WidthData NUMERIC "8" -- Retrieval info: PRIVATE: WidthAddr NUMERIC "4" -- Retrieval info: PRIVATE: Clock NUMERIC "3" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1" -- Retrieval info: PRIVATE: REGrren NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: UseLCs NUMERIC "0" -- Retrieval info: CONSTANT: WIDTH NUMERIC "8" -- Retrieval info: CONSTANT: WIDTHAD NUMERIC "4" -- Retrieval info: CONSTANT: INDATA_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: WRADDRESS_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: WRCONTROL_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: RDADDRESS_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: RDCONTROL_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: OUTDATA_REG STRING "UNREGISTERED" -- Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF" -- Retrieval info: CONSTANT: WRADDRESS_ACLR STRING "OFF" -- Retrieval info: CONSTANT: WRCONTROL_ACLR STRING "OFF" -- Retrieval info: CONSTANT: RDADDRESS_ACLR STRING "OFF" -- Retrieval info: CONSTANT: RDCONTROL_ACLR STRING "OFF" -- Retrieval info: CONSTANT: OUTDATA_ACLR STRING "OFF" -- Retrieval info: CONSTANT: LPM_HINT STRING "USE_EAB=ON" -- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0] -- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] -- Retrieval info: USED_PORT: wraddress 0 0 4 0 INPUT NODEFVAL wraddress[3..0] -- Retrieval info: USED_PORT: rdaddress 0 0 4 0 INPUT NODEFVAL rdaddress[3..0] -- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT VCC wren -- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 -- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 -- Retrieval info: CONNECT: @wraddress 0 0 4 0 wraddress 0 0 4 0 -- Retrieval info: CONNECT: @rdaddress 0 0 4 0 rdaddress 0 0 4 0 -- Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0