-------------------------------------------------------------------------------
--
-- ffttestjig.vhd: test jig for validating FFT processor
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/05
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity ffttestjig is

    port (
    start, reset, clk         : in    std_logic;
    busy                      : out   std_logic;
    inbufsel, outbufsel       : in    std_logic_vector(1 downto 0);
    treout                    : out   std_logic_vector(7 downto 0);
    databusinout              : out   std_logic_vector(7 downto 0);
    databusoutout             : out   std_logic_vector(7 downto 0);
    inverse                   : in    std_logic;
    ramwe                     : out   std_logic);
  
end ffttestjig;

architecture structural of ffttestjig is

  component fft
    port (
    start, reset, clk         : in    std_logic;
    testaddrbus                   : out   std_logic_vector(6 downto 0);
    databusout                   : out std_logic_vector(7 downto 0);
    databusin                   : in std_logic_vector(7 downto 0);
    busy                      : out   std_logic;
    inbufsel, outbufsel       : in    std_logic_vector(1 downto 0);
    treout                    : out   std_logic_vector(7 downto 0);
    databusinout              : out   std_logic_vector(7 downto 0);
    inverse                   : in    std_logic;
    ramwe                     : out   std_logic);

  end component;

--  component testram
--        PORT
--        (
--                address         : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--                we              : IN STD_LOGIC  := '1';
--                outenab         : IN STD_LOGIC  := '1';
--                dio             : INOUT STD_LOGIC_VECTOR (13 DOWNTO 0)
--        );
--  end component;
--
 component testram
       PORT
       (
               address         : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
               we              : IN STD_LOGIC  := '1';
               data            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
               q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
       );
end component;
  
  signal addrbus : std_logic_vector(6 downto 0);
  signal databus, d, q : std_logic_vector(7 downto 0);
  signal fftwe, oe, ramweint : std_logic;
  
begin  -- structural


  fftinst : fft port map (
    start     => start,
    reset     => reset,
    clk       => clk,
    testaddrbus   => addrbus,
    databusout   => d,
    databusin => q,
    busy      => busy,
    inbufsel  => inbufsel,
    outbufsel => outbufsel,
    treout    => treout,
    inverse   => inverse,
    databusinout => databusinout,
    ramwe     => fftwe);

  raminst : testram port map (
    address   => addrbus,
    data        => d,
    q   => q,
    we        => ramweint);


  oe <= '1';
  ramweint <= fftwe and not clk;

  ramwe <= ramweint;

  databusoutout <= d;

end structural;