library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ramfsmtest is
  port(clk, reset                    : in std_logic;
       complexgood, who, start       : in std_logic; -- in from readFSM
       run, page                     : out std_logic; -- out to writeFSM
       frame                         : out std_logic; -- out to MUX Control
       BUFFERwe                      : out std_logic; -- out to buffer
       whopass                       : out std_logic;
       offset                        : out std_logic_vector(4 downto 0);
       BUFFERaddress                 : out std_logic_vector(3 downto 0);
       complexin                     : in std_logic_vector(16 downto 0); -- out to D/A
       BUFFERout                     : out std_logic_vector(7 downto 0)); -- out to Buffer RAM

end ramfsmtest;

architecture behavioral of ramfsmtest is

  type StateType is (clear, idle, waitstate, read1, read2, downsample, writebuffer1, writebuffer2, writebuffer3,
                     runstate, skipstate1, skipstate2);
  attribute enum_encoding : string;
  attribute enum_encoding of StateType:
    type is "0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011";
  -- 0000 = clear
  -- 0010 = idle
  -- 0011 = waitstate
  -- 0100 = read
  -- 0101 = downsample
  -- 0110 = writebuffer

  signal p_s, n_s : StateType;

  signal accumulate, accumulate0                               : std_logic_vector(23 downto 0);
  signal BUFFout, BUFFout0                                     : std_logic_vector(7 downto 0);
  signal column, column0                                       : std_logic_vector(4 downto 0);
  signal BUFFadd, BUFFadd0, skipcount, skipcount0              : std_logic_vector(3 downto 0);
  signal averagecount, averagecount0, samples, samples0        : std_logic_vector(2 downto 0);
  signal wholatch, wholatch0, BUFFpage, BUFFpage0              : std_logic;
  signal frameout, frameout0, run0                             : std_logic;



begin

  frame <= frameout;
  BUFFERaddress <= BUFFadd;
  BUFFERout <= BUFFout;
  page <= BUFFpage;
  offset <= column;
  whopass <= wholatch;

  clocked:process(clk)
  begin
    if clk'event and clk = '1' then
      if reset = '1' then
        p_s <= clear;
      else p_s <= n_s;
      end if;
      accumulate <= accumulate0;
      averagecount <= averagecount0;
      samples <= samples0;
      skipcount <= skipcount0;
      wholatch <= wholatch0;
      column <= column0;
      frameout <= frameout0;
      BUFFpage <= BUFFpage0;
      run <= run0;
      BUFFadd <= BUFFadd0;
      BUFFout <= BUFFout0;
    end if;
  end process;

  states:process(p_s, n_s)
  begin
    case p_s is
      when clear =>                      -- 0000
        run0 <= '0';
        accumulate0 <= "000000000000000000000000";
        samples0 <= "000";
        averagecount0 <= "000";
        column0 <= "00010";
        frameout0 <= '0';
        BUFFpage0 <= '0';
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        BUFFERwe <= '0';
        skipcount0 <= "0000";
        wholatch0 <= '0';

        n_s <= idle;
            
      when idle =>                       -- 0001
        run0 <= '0';
        accumulate0 <= "000000000000000000000000";
        samples0 <= "000";
        averagecount0 <= "000";
        BUFFpage0 <= '0';
        column0 <= "00010";
        frameout0 <= frameout;
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        BUFFERwe <= '0';
        skipcount0 <= "0000";
        wholatch0 <= '0';
        
        if start = '1' then
          n_s <= waitstate;
        else n_s <= p_s;
        end if;
      
      when waitstate=>                   -- 0010
        run0 <= '0';
        accumulate0 <= accumulate;
        samples0 <= samples;
        averagecount0 <= averagecount;
        BUFFpage0 <= BUFFpage;
        column0 <= column;
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        BUFFERwe <= '0';
        wholatch0 <= wholatch;

        if start = '0' then
          if wholatch = '1' then
            frameout0 <= not frameout;
            n_s <= idle;
          else frameout0 <= frameout;
            n_s <= p_s;
          end if;
        elsif complexgood = '1' then
          frameout0 <= frameout;
          n_s <= read1;
        else frameout0 <= frameout;
          n_s <= p_s;
        end if;

      when read1 =>                       -- 0011
        run0 <= '0';
        column0 <= column;
        BUFFpage0 <= BUFFpage;
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        samples0 <= samples;
        accumulate0 <= ("0000000" & complexin) + accumulate;
        averagecount0 <= averagecount + 1;
        wholatch0 <= who;
        
        n_s <= read2;

      when read2 =>                    -- 0100
        run0 <= '0';
        column0 <= column;
        samples0 <= samples;
        BUFFERwe <= '0';
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        accumulate0 <= accumulate;
        averagecount0 <= averagecount;
        wholatch0 <= wholatch;
        
        if averagecount = "110" then
          n_s <= downsample;
        elsif complexgood = '0' then
          n_s <= waitstate;
        else n_s <= p_s;
        end if;

      when downsample =>               -- 0101
        run0 <= '0';
        column0 <= column;        
        averagecount0 <= "000";
        samples0 <= samples;
        accumulate0 <= accumulate + ( accumulate(22 downto 0) & '0');
          -- divide by 6 to average + multiply by 18 to scale = multiply by 3
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        wholatch0 <= wholatch;
          
        n_s <= writebuffer1;

      when writebuffer1 =>             -- 0110
        run0 <= '0';
        column0 <= column;        
        accumulate0 <= accumulate;
        BUFFadd0 <= BUFFpage & samples;
        BUFFout0 <= accumulate(23 downto 16);
        BUFFERwe <= '0';
        samples0 <= samples;
        wholatch0 <= wholatch;
        
        n_s <= writebuffer2;

      when writebuffer2 =>             -- 0111
        run0 <= '0';
        column0 <= column;        
        accumulate0 <= accumulate;
        BUFFadd0 <= BUFFadd;
        BUFFout0 <= BUFFout;
        BUFFERwe <= '1';
        samples0 <= samples;
        wholatch0 <= wholatch;
        
        n_s <= writebuffer3;

      when writebuffer3 =>             -- 1000
        column0 <= column;        
		accumulate0 <= "000000000000000000000000";
        BUFFadd0 <= BUFFadd;
        BUFFout0 <= BUFFout;
        BUFFERwe <= '0';
        samples0 <= samples;
        wholatch0 <= wholatch;

        if samples = "111" then
          run0 <= '1';
        else run0 <= '0';
        end if;

        n_s <= runstate;

      when runstate =>                       -- 1001
        run0 <= '0';
        accumulate0 <= accumulate;
        BUFFadd0 <= "0000";
        BUFFout0 <= "00000000";
        BUFFERwe <= '0';
        wholatch0 <= wholatch;
        
        if column = "10110" then
          if samples = "111" then
            column0 <= "00010";
            samples0 <= "000";
            BUFFpage0 <= not BUFFpage;
            n_s <= skipstate1;
          else column0 <= column;
            samples0 <= samples + 1;
            BUFFpage0 <= BUFFpage;
            n_s <= read1;
          end if;
        elsif samples = "111" then
          column0 <= column + 1;
          samples0 <= "000";
          BUFFpage0 <= not BUFFpage;
          n_s <= read1;
        else column0 <= column;
          samples0 <= samples + 1;
          BUFFpage0 <= BUFFpage;
          n_s <= read1;
        end if;

      when skipstate1 =>                -- 1010
        BUFFERwe <= '0';
        wholatch0 <= wholatch;
        column0 <= "00010";
        samples0 <= "000";
        skipcount0 <= skipcount;
        if complexgood = '1' then
          n_s <= skipstate2;
        else n_s <= p_s;
        end if;

      when skipstate2 =>                -- 1011
        BUFFERwe <= '0';
        wholatch0 <= wholatch;
        column0 <= "00010";
        samples0 <= "000";
        if complexgood = '0' then
          if skipcount = "1111" then
            skipcount0 <= "0000";
            n_s <= waitstate;
          else skipcount0 <= skipcount + 1;
            n_s <= skipstate1;
          end if;
        else skipcount0 <= skipcount;
          n_s <= p_s;
        end if;

    end case;

  end process states;
end architecture behavioral;