-------------------------------------------------------------------------------
--
-- ramtest.vhd : ram test
-- Dan R. K. Ports  <drkp@mit.edu>
-- 6.111 final project, 2003/12/09
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity ramtest is
  
  port (
    clk  : in    std_logic;
    addr : out   std_logic_vector(13 downto 0);
    ok   : out   std_logic;
    datab : inout std_logic_vector(7 downto 0);
    n_we : out   std_logic);

end ramtest;

architecture behavioral of ramtest is

  signal addrbuf : std_logic_vector(3 downto 0);
  signal flag : std_logic;
  signal buf : std_logic_vector(7 downto 0);
  
begin  -- behavioral


  process (clk)
  begin  -- process
    if rising_edge(clk) then
      addrbuf <= addrbuf + 1;
      if addrbuf = "1111" then
        flag <= not flag;
      end if;
      if flag = '1' then
      else
        buf <= datab;
      end if;
    end if;
  end process;

  datab <= "0000" & (addrbuf + 1) when flag = '1' else (others => 'Z');

  addr <= "0000000000" & addrbuf;
  n_we <= not flag;

  ok <= '1' when flag = '1' or (buf = ("0000" & addrbuf)) else '0';

end behavioral;