library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity readfsmtest is
  port(clk, reset                              : in std_logic;
       DANenable, DANready                     : in std_logic;
       ANDREWenable, ANDREWready               : in std_logic;
       ACK, start                              : out std_logic;
       who, complexready                       : out std_logic; -- out to RAMfsm
       complex			                       : out std_logic_vector(16 downto 0); -- out to RAMfsm
       BUSin                                   : in std_logic_vector(7 downto 0)); -- in from Parallel BUS
end readfsmtest;

architecture behavioral of readfsmtest is

  type StateType is (clear, idle, waitdata, readdata1, readdata2);
  attribute enum_encoding : string;
  attribute enum_encoding of StateType:
    type is "000 001 010 011 100";
  -- 000 clear
  -- 001 idle
  -- 010 waitdata
  -- 011 readdata1
  -- 100 readdata2

  signal p_s, n_s : StateType;

  signal complex_r, complex_i  : std_logic_vector(7 downto 0);
  signal delay, delay0         : std_logic_vector(3 downto 0);
  signal count, count0         : std_logic_vector(11 downto 0);
  signal complexlatch, complexlatch0          : std_logic_vector(16 downto 0);
  signal valid, dataready, cready, cready0      : std_logic;

begin


  valid <= DANenable xor ANDREWenable;
  complex <= complexlatch;
  complexready <= cready;

  clocked:process(clk)
  begin
    if clk'event and clk = '1' then
      if reset = '1' then
        p_s <= clear;
      else p_s <= n_s;
      delay <= delay0;
      count <= count0;
      complexlatch <= complexlatch0;
      cready <= cready0;
      end if;

    if DANenable = '1' then
      who <= '0';
      dataready <= DANready;
    elsif ANDREWenable = '1' then
      who <= '1';
      dataready <= ANDREWready;
    else who <= '0';
      dataready <= '0';
    end if;



    end if;
  end process;
  
  states:process(p_s, n_s, count, delay, complexlatch, complexlatch0, valid, dataready, count0, BUSin, DAnenable, ANDREWenable)
  begin
    case p_s is
      when clear =>                  -- 000
        count0 <= "000000000000";
        delay0 <= "0000";
        complexlatch0 <= "00000000000000000";
        start <= '0';
        ACK <= '0';
        cready0 <= '0';
        n_s <= idle;

      when idle =>                   -- 001
        ACK <= '0';
        start <= '0';
        count0 <= "000000000000";
        complexlatch0 <= "00000000000000000";
        cready0 <= '0';
        delay0 <= "0000";
        if valid = '1' then
          n_s <= waitdata;
        else n_s <= p_s;
        end if;

      when waitdata =>               -- 010
        complexlatch0 <= complexlatch;
        count0 <= count;
        cready0 <= '0';
        ACK <= '0';
        delay0 <= delay + 1;
        if valid = '1' then
          start <= '1';
          if dataready = '1' then
            n_s <= readdata1;
          else n_s <= p_s;
          end if;
        else
          start <= '0';      
          if delay = "1111" then
            n_s <= idle;
          else n_s <= p_s;
          end if;
        end if;

      when readdata1 =>               -- 011
        delay0 <= "0000";
        complexlatch0 <= complexlatch;           
        if count(0) = '0' then
          cready0 <= '0';
          if BUSin(7) = '0' then
            complex_r <= BUSin;
          else complex_r <= not(BUSin) + 1;
          end if;
        else
          cready0 <= '1';
          if BUSin(7) = '0' then
            complex_i <= BUSin;
          else complex_i <= not(BUSin) + 1;
          end if;
          complexlatch0 <= (("000000000" & complex_r) * ("000000000" & complex_r)) + (("000000000" & complex_i) * ("000000000" & complex_i));
        end if;
        ACK <= '1';
        count0 <= count + 1;
        n_s <= readdata2;

      when readdata2 =>          -- 100
        ACK <= '1';
        start <= '1';
        count0 <= count;
        complexlatch0 <= complexlatch;
        cready0 <= cready;
        if dataready = '0' then
          n_s <= waitdata;
        else n_s <= p_s;
        end if;

    end case;
  end process states;

end architecture behavioral;