library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity top is
  port(clk, reset        	           	  : in std_logic;
       DAN, DANr, ANDREW, ANDREWr         : in std_logic;
       ACK, MUXcontrol                    : out std_logic;
       BUSinline                          : in std_logic_vector(7 downto 0);
       nwren, nouten                      : out std_logic;
       RAMaddress                         : out std_logic_vector(12 downto 0);
       tstate                             : out std_logic_vector(12 downto 0);
       RAMdata                            : out std_logic_vector(7 downto 0)
-- DEBUG
--;
--goodsignal : out std_logic;
--runrunrun: out std_logic;
--pager : out std_logic
-- DEBUG
       );
end top;

architecture testing of top is

component readfsmtest
  port(clk, reset                              : in std_logic;
       DANenable, DANready                     : in std_logic;
       ANDREWenable, ANDREWready               : in std_logic;
       ACK                                     : out std_logic;
       who, complexready, start                : out std_logic; -- out to RAMfsm
       complex			                       : out std_logic_vector(16 downto 0); -- out to RAMfsm
       BUSin                                   : in std_logic_vector(7 downto 0)); -- in from Parallel BUS
end component;

component ramfsmtest
  port(clk, reset                    : in std_logic;
       complexgood, who, start       : in std_logic; -- in from readFSM
       run, page                     : out std_logic; -- out to writeFSM
       frame                         : out std_logic; -- out to MUX Control
       BUFFERwe                      : out std_logic; -- out to buffer
       offset                        : out std_logic_vector(5 downto 0);
       BUFFERaddress                 : out std_logic_vector(3 downto 0);
       complexin                     : in std_logic_vector(16 downto 0); -- out to D/A
       BUFFERout                     : out std_logic_vector(7 downto 0)); -- out to Buffer RAM
end component;

component writefsmtest2
  port(clk, reset                  : in std_logic;
       run, page                   : in std_logic; -- in from ramFSM
       BUFFERaddress               : out std_logic_vector(3 downto 0); -- out to buffer RAM
       BUFFERin                    : in std_logic_vector(7 downto 0); -- in from Buffer
       offset                      : in std_logic_vector(5 downto 0); -- in from ramFSM
       nWE, nOE                    : out std_logic; -- out to video RAMs
       RAMaddress                  : out std_logic_vector(12 downto 0); -- out to video RAMs
       RAMout                      : out std_logic_vector(7 downto 0)); -- out to video RAMs
end component;

component buff IS
	PORT
	(
		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
		wraddress		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		rdaddress		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
		wren		: IN STD_LOGIC  := '1';
		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
	);
END component;


--  COMPONENT ROM
--	PORT(address                            : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
--         inclock                          : IN STD_LOGIC;
--         outclock                         : IN STD_LOGIC ;
--         q                                : OUT STD_LOGIC_VECTOR (24 DOWNTO 0));
--  END COMPONENT;

  signal whosignal, startsignal                          : std_logic;
  signal wrenable, complexsignal, runsignal, pagesignal  : std_logic;
  signal offsetsignal, who                               : std_logic_vector(5 downto 0);
  signal BUFFaddress, writeaddress                       : std_logic_vector(3 downto 0);
  signal XMsecond, BUFFin, dataline                      : std_logic_vector(7 downto 0);
  signal complexdataline                                 : std_logic_vector(16 downto 0);

begin


tstate <= "ZZZZZZZZZZZZZ";

--clk <= clksignal;
--resetsignal <= reset;

-- DEBUG
--goodsignal <= complexsignal;
--runrunrun <= runsignal;
--pager <= pagesignal;
-- DEBUG

READER:readfsmtest
  port map(clk => clk,
           reset => reset,
           DANenable => DAN,
           DANready => DANr,
           ANDREWenable => ANDREW,
           ANDREWready => ANDREWr,
           ACK => ACK,
           who => whosignal,
           complexready => complexsignal,
           start => startsignal,
           complex => complexdataline,
           BUSin => BUSinline);

RAMMER:ramfsmtest
  port map(clk => clk,
           reset => reset,
           complexgood => complexsignal,
           who => whosignal,
           start => startsignal,
           run => runsignal,
           page => pagesignal,
           frame => MUXcontrol,
           BUFFERwe => wrenable,
           offset => offsetsignal,
           BUFFERaddress => writeaddress,
           complexin => complexdataline,
           BUFFERout => dataline);

WRITER:writefsmtest2
  port map(clk => clk,
           reset => reset,
           run => runsignal,
           page => pagesignal,
           BUFFERaddress => BUFFaddress,
           BUFFERin => BUFFin,
           offset => offsetsignal,
           nWE => nwren,
           nOE => nouten,
           RAMaddress => RAMaddress,
           RAMout => RAMdata);

BUFFERER:buff
  PORT map(data => dataline,
		   wraddress => writeaddress,
           rdaddress => BUFFaddress,
           wren => wrenable,
           q => BUFFin);

end architecture testing;