-------------------------------------------------------------------------- -- -- top.vhd: top-level structural definition -- Dan R. K. Ports -- 6.111 final project, 2003/12/08 -- -------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; entity top is port ( clk, reset : in std_logic; n_DACEnable, n_ADCEnable, ADCRead : out std_logic; ADCStatus : in std_logic; adbus : inout std_logic_vector(7 downto 0); fftsending, fftrdyack : out std_logic; procsending, procrdyack, ack2 : in std_logic; ramaddr : out std_logic_vector(13 downto 0); -- ramdatain : in std_logic_vector(7 downto 0); -- ramdataout : out std_logic_vector(7 downto 0); ramdata : inout std_logic_vector(7 downto 0); n_ramwe : out std_logic; adtest, ffttest : in std_logic; curportout : out std_logic_vector(1 downto 0); ifdatabus : inout std_logic_vector(7 downto 0)); end top; architecture structural of top is component adfsm port ( clk, start : in std_logic; reset : in std_logic; timerClk : in std_logic; busy : out std_logic; ADCRead, n_DACEnable : out std_logic; n_ADCEnable : out std_logic; ADCStatus : in std_logic; ramwe : out std_logic; ramaddr : out std_logic_vector(13 downto 0); ramdatain : in std_logic_vector(7 downto 0); ramdataout : out std_logic_vector(7 downto 0); adcbufsel : in std_logic_vector(2 downto 0); dacbufsel : in std_logic_vector(2 downto 0); ramreq : out std_logic; ramdone : in std_logic; adbus : inout std_logic_vector(7 downto 0)); end component; component control port ( reset, clk : in std_logic; adstart, fftstart, ifstart : out std_logic; adbusy, fftbusy, ifbusy : in std_logic; adtest, ffttest : in std_logic; fftinverse : out std_logic; adcbufsel, dacbufsel, fftinbufsel, fftoutbufsel, ifsendbufsel, ifrecvbufsel : out std_logic_vector(2 downto 0)); end component; component divider port ( clk, rst : in std_logic; longclk : out std_logic); end component; component fft port ( start, reset, clk : in std_logic; addrbus : out std_logic_vector(13 downto 0); testaddrbus : out std_logic_vector(6 downto 0); -- databus : inout std_logic_vector(7 downto 0); databusout : out std_logic_vector(7 downto 0); databusin : in std_logic_vector(7 downto 0); busy : out std_logic; inbufsel, outbufsel : in std_logic_vector(2 downto 0); inverse : in std_logic; treout,timout,breout,bimout, wbreout, wbimout : out std_logic_vector(7 downto 0); databusinout : out std_logic_vector(7 downto 0); nextiout : out std_logic_vector(9 downto 0); copyimout : out std_logic; ramreq : out std_logic; ramdone : in std_logic; ramwe : out std_logic); end component; component interfacefsm port ( start : in std_logic; reset : in std_logic; busy : out std_logic; sendbufsel, recvbufsel : in std_logic_vector(2 downto 0); clk : in std_logic; fftsending : out std_logic; procsending : in std_logic; fftrdyack : out std_logic; procrdyack : in std_logic; ack2 : in std_logic; ramaddr : out std_logic_vector(13 downto 0); ramdatain : in std_logic_vector(7 downto 0); ramdataout : out std_logic_vector(7 downto 0); databus : inout std_logic_vector(7 downto 0); ramreq : out std_logic; ramdone : in std_logic; ramwe : out std_logic); end component; component memmgr port ( aaddr, baddr, caddr : in std_logic_vector(14-1 downto 0); adata, bdata, cdata : in std_logic_vector(8-1 downto 0) := (others => 'Z'); aq, bq, cq : out std_logic_vector(8-1 downto 0) := (others => 'Z'); awr, bwr, cwr : in std_logic; clk, reset : in std_logic; areq, breq, creq : in std_logic; adone, bdone, cdone : out std_logic; ramaddr : out std_logic_vector(14-1 downto 0); ramdata : inout std_logic_vector(8-1 downto 0) := (others => 'Z'); -- ramdatain : in std_logic_vector(7 downto 0); -- ramdataout : out std_logic_vector(7 downto 0); curportout : out std_logic_vector(1 downto 0); ramwe : out std_logic); end component; component synchronizer1 port ( clk, syncin : in std_logic; syncout : out std_logic); end component; signal adstart, adbusy, fftstart, fftbusy, ifstart, ifbusy, timerClk, awr, bwr, cwr, areq, breq, creq, adone, bdone, cdone : std_logic; signal aaddr, baddr, caddr : std_logic_vector(13 downto 0); signal ad, bd, cd, aq, bq, cq : std_logic_vector(7 downto 0); signal adcbufsel, dacbufsel, fftinbufsel, fftoutbufsel, ifsendbufsel, ifrecvbufsel : std_logic_vector(2 downto 0); signal fftinverse, procsendingsync, procrdyacksync, ack2sync : std_logic; signal ramwe : std_logic; begin -- structural adfsminst : adfsm port map ( clk => clk, start => adstart, reset => reset, timerClk => timerClk, busy => adbusy, ADCRead => ADCRead, n_DACEnable => n_DACEnable, n_ADCEnable => n_ADCEnable, ADCStatus => ADCStatus, ramwe => bwr, ramaddr => baddr, ramdatain => bq, ramdataout => bd, adcbufsel => adcbufsel, dacbufsel => dacbufsel, ramreq => breq, ramdone => bdone, adbus => adbus); controlinst : control port map ( reset => reset, clk => clk, adtest => adtest, ffttest => ffttest, adstart => adstart, fftstart => fftstart, ifstart => ifstart, adbusy => adbusy, fftbusy => fftbusy, ifbusy => ifbusy, fftinverse => fftinverse, adcbufsel => adcbufsel, dacbufsel => dacbufsel, fftinbufsel => fftinbufsel, fftoutbufsel => fftoutbufsel, ifsendbufsel => ifsendbufsel, ifrecvbufsel => ifrecvbufsel); dividerinst : divider port map ( clk => clk, rst => reset, longclk => timerClk); fftinst : fft port map ( start => fftstart, reset => reset, clk => clk, addrbus => aaddr, databusout => ad, databusin => aq, busy => fftbusy, inbufsel => fftinbufsel, outbufsel => fftoutbufsel, inverse => fftinverse, ramreq => areq, ramdone => adone, ramwe => awr); ifinst : interfacefsm port map ( start => ifstart, reset => reset, busy => ifbusy, sendbufsel => ifsendbufsel, recvbufsel => ifrecvbufsel, clk => clk, fftsending => fftsending, procsending => procsendingsync, fftrdyack => fftrdyack, procrdyack => procrdyacksync, ack2 => ack2sync, ramaddr => caddr, ramdatain => cq, ramdataout => cd, databus => ifdatabus, ramreq => creq, ramdone => cdone, ramwe => cwr); memmgrinst : memmgr port map ( aaddr => aaddr, baddr => baddr, caddr => caddr, adata => ad, bdata => bd, cdata => cd, aq => aq, bq => bq, cq => cq, awr => awr, bwr => bwr, cwr => cwr, clk => clk, reset => reset, areq => areq, breq => breq, creq => creq, adone => adone, bdone => bdone, cdone => cdone, ramaddr => ramaddr, -- ramdatain => ramdatain, -- ramdataout => ramdataout, ramdata => ramdata, curportout => curportout, ramwe => ramwe); syncprocsending : synchronizer1 port map ( clk => clk, syncin => procsending, syncout => procsendingsync); syncprocrdyack : synchronizer1 port map ( clk => clk, syncin => procrdyack, syncout => procrdyacksync); syncack2 : synchronizer1 port map ( clk => clk, syncin => ack2, syncout => ack2sync); n_ramwe <= not ramwe; end structural;