-- twiddler16.vhd: 16-bit twiddle factor generator
-- Dan R. K. Ports <drkp@mit.edu>
-- 6.111 final project, 2003/12/05

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;

entity twiddler16 is
  
  port (
    twiddlesel : in  std_logic_vector(8 downto 0);
    twiddlere, twiddleim  : out std_logic_vector(7 downto 0));

end twiddler16;

architecture structural of twiddler16 is

  component twiddlerom16c
        PORT
        (
                address         : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
  end component;


  component twiddlerom16s
        PORT
        (
                address         : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
                q               : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
        );
  end component;

  
begin  -- structural

  sinrom : twiddlerom16s port map (
    address => twiddlesel(3 downto 0),
    q       => twiddleim);

  cosrom : twiddlerom16c port map (
    address => twiddlesel(3 downto 0),
    q       => twiddlere);
  
end structural;