library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity writefsmtest2 is
  port(clk, reset                  : in std_logic;

--direct inputs
--     switch1, switch2, switch3   : in std_logic_vector(3 downto 0);
--     mode                        : in std_logic_vector(1 downto 0);

       run, page                   : in std_logic; -- in from ramFSM
       BUFFERaddress               : out std_logic_vector(3 downto 0); -- out to buffer RAM
       BUFFERin                    : in std_logic_vector(7 downto 0); -- in from Buffer
       offset                      : in std_logic_vector(4 downto 0); -- in from ramFSM
       whopass                     : in std_logic; -- in from ramFSM
       nWE, nOE                    : out std_logic; -- out to video RAMs
       RAMaddress                  : out std_logic_vector(12 downto 0); -- out to video RAMs
       RAMout                      : out std_logic_vector(7 downto 0)); -- out to video RAMs
end writefsmtest2;

architecture behavioral of writefsmtest2 is

  type StateType is (clear, idle, readin1, readin2, drawgraph1, addressstate, drawgraph2);
  attribute enum_encoding : string;
  attribute enum_encoding of StateType:
    type is "000 001 010 011 100 101 110";
  -- 000 = clear
  -- 001 = idle
  -- 010 = readin1
  -- 011 = readin2
  -- 100 = drawgraph1
  -- 101 = drawgraph2


  signal p_s, n_s : StateType;

  signal RAMaddress0                                          : std_logic_vector(12 downto 0);
  signal piece, RAMout0, RAMout1, s0, s1, s2, s3, s4, s5, s6, s7       : std_logic_vector(7 downto 0);
  signal count, count0                                        : std_logic_vector(6 downto 0);
  signal lowcount, lowcount0                                  : std_logic_vector(3 downto 0);
  signal rowcount, rowcount0                                  : std_logic_vector(2 downto 0);
  signal tick, tick0                                          : std_logic_vector(2 downto 0);
  signal pagelatch, pagelatch0, wholatch, wholatch0           : std_logic;
  signal nWElatch, nWElatch0, nOElatch, nOElatch0             : std_logic;

begin

  nWE <= nWElatch;
  nOE <= nOElatch;
  RAMout <= RAMout1;

  clocked:process(clk)
  begin
    if clk'event and clk = '1' then
      if reset = '1' then
        p_s <= clear;
      else count <= count0;
        tick <= tick0;
        lowcount <= lowcount0;
        rowcount <= rowcount0;
--        RAMout <= RAMout0;
RAMout1 <= RAMout0;
        RAMaddress <= RAMaddress0;
        pagelatch <= pagelatch0;
        wholatch <= wholatch0;
        nWElatch <= nWElatch0;
        nOElatch <= nOElatch0;
        p_s <= n_s;
      end if;
    end if;
  end process;

  states:process(p_s, n_s, lowcount0, lowcount, rowcount0, rowcount, tick, tick0, wholatch, wholatch0,
                 whopass, count, count0, s0, s1, s2, s3, s4,  s5, s6, s7, piece,  BUFFERin, offset,
                 run, page, RAMaddress0, RAMout0, nWElatch, nWElatch0, nOElatch, nOElatch0)
  begin
    case p_s is
    
      when clear =>                    -- 0000
        tick0 <= "000";
        count0 <= "1001000";
        lowcount0 <= "0000";
        rowcount0 <= "001";
        RAMaddress0 <= "0000000000000";
        RAMout0 <= "00000000";
        pagelatch0 <= '0';
        wholatch0 <= '0';
        nWElatch0 <= '1';
        nOElatch0 <= '1';
        
        n_s <= idle;
        
      when idle =>                     -- 0001
        tick0 <= "000";
        count0 <= "1001000";
        lowcount0 <= lowcount;
        rowcount0 <= rowcount;
        RAMaddress0 <= "0000000000000";
        RAMout0 <= "00000000";
        BUFFERaddress <= "0000";

        if run = '1' then
          pagelatch0 <= page;
          wholatch0 <= whopass;
          n_s <= readin1;
        else pagelatch0 <= '0';
          wholatch0 <= '0';
          n_s <= p_s;
        end if;

      when readin1 =>                   -- 0010
        tick0 <= tick;
        count0 <= count;
        lowcount0 <= lowcount;
        rowcount0 <= rowcount;
        RAMaddress0 <= "0000000000000";
        RAMout0 <= "00000000";
        BUFFERaddress <= pagelatch & tick;
        pagelatch0 <= pagelatch;
        nWElatch0 <= '1';
        nOElatch0 <= '1';
        piece <= "00000000";

        n_s <= readin2;

      when readin2 =>                    -- 0011
        count0 <= count;
        lowcount0 <= lowcount;
        rowcount0 <= rowcount;
        RAMaddress0 <= "0000000000000";
        RAMout0 <= "00000000";
        BUFFERaddress <= pagelatch & tick;
        pagelatch0 <= pagelatch;
        nWElatch0 <= '1';
        nOElatch0 <= '1';
        piece <= "00000000";

        tick0 <= tick + 1;

        case tick is
          when "000" =>
            s0 <= BUFFERin;
            n_s <= readin2;
          when "001" => 
            s1 <= BUFFERin;
            n_s <= readin2;
          when "010" =>
            s2 <= BUFFERin;
            n_s <= readin2;
          when "011" =>
            s3 <= BUFFERin;
            n_s <= readin2;
          when "100" =>
            s4 <= BUFFERin;
            n_s <= readin2;
          when "101" =>
            s5 <= BUFFERin;
            n_s <= readin2;
          when "110" =>
            s6 <= BUFFERin;
            n_s <= readin2;
          when "111" =>
            s7 <= BUFFERin;
            n_s <= drawgraph1;
          when others =>
            null;
        end case;      
        
      when drawgraph1 =>                -- 0100

        if count > s0 then
          piece(0) <= '0';
        else piece(0) <= '1';
        end if;
        if count > s1 then
          piece(1) <= '0';
        else piece(1) <= '1';
        end if;
        if count > s2 then
          piece(2) <= '0';
        else piece(2) <= '1';
        end if;
        if count > s3 then
          piece(3) <= '0';
        else piece(3) <= '1';
        end if;
        if count > s4 then
          piece(4) <= '0';
        else piece(4) <= '1';
        end if;
        if count > s5 then
          piece(5) <= '0';
        else piece(5) <= '1';
        end if;
        if count > s6 then
          piece(6) <= '0';
        else piece(6) <= '1';
        end if;
        if count > s7 then
          piece(7) <= '0';
        else piece(7) <= '1';
        end if;
        
        tick0 <= "000";
        count0 <= count - 1;
        lowcount0 <= lowcount;
        rowcount0 <= rowcount;
        RAMaddress0 <= (((wholatch & rowcount) & offset) & lowcount);
        RAMout0 <= piece;
        BUFFERaddress <= "0000";
        pagelatch0 <= pagelatch;
        nWElatch0 <= '1';
        nOElatch0 <= '1';

        n_s <= addressstate;

      when addressstate =>                  -- 0101
        tick0 <= tick;
        count0 <= count;
        lowcount0 <= lowcount;
        rowcount0 <= rowcount;
        RAMaddress0 <= (((wholatch & rowcount) & offset) & lowcount);
--        RAMout0 <= piece;
        BUFFERaddress <= "0000";
        pagelatch0 <= pagelatch;
        nWElatch0 <= '0';
        nOElatch0 <= '0';

        n_s <= drawgraph2;

      when drawgraph2 =>          -- 0110
        tick0 <= tick;
        count0 <= count;
        RAMaddress0 <= (((wholatch & rowcount) & offset) & lowcount);
--        RAMout0 <= piece;
        BUFFERaddress <= "0000";
        pagelatch0 <= pagelatch;
        nWElatch0 <= '1';
        nOElatch0 <= '1';

        if lowcount = "1011" then
          if count = "0000000" then
            lowcount0 <= "0000";
            rowcount0 <= "001";
            n_s <= idle;
          else lowcount0 <= "0000";
            rowcount0 <= rowcount + 1;
            n_s <= readin1;
          end if;
        else lowcount0 <= lowcount + 1;
          rowcount0 <= rowcount;
          n_s <= drawgraph1;
        end if;
    end case;
  end process states;
end architecture behavioral;